Workshop on FPGA

Workshop on FPGA

The National Centre for Physics has organized a 3-day FPGA workshop from 14th – 16th February, 2006.

The workshop aims were to impart the participants a good understanding about FPGAs & their significance in the field of advance digital design by delivering lectures & providing them hands on practice on FPGA development boards. After the completion of this workshop, the participants got good knowledge of the basic architecture of FPGA & CPLD & were able to program the FPGA according to their desired digital design.

The event covered these topics in lectures:

• Digital Design Objective

• Clock Methodology, Critical & Cycle Time

• Verilog HDL Basics, Abstraction Levels

• Module Basics, Module Instances

• Hierarchal Design

• Gate Level Modeling

• Data-Flow: Continuous Assignments

• Operators

• Behavioral Modeling

• Procedural Blocks (initial, always)

• Blocking & Non-Blocking Assignments

• Clock & Async/Sync Reset in Digital System

• Built-in-Self Test (BIST) in chips

• Boundary Scan Testing

• Digital Systems, State Machine Concept

• RTL Coding Guidelines

• Introduction of FPGA

• Xilinx FPGA Basics

• Xilinx FPGA CLBs

• LUT Implementation in CLBs, FPGA I/O Blocks

• Xilinx XC4000 and Spartan Series FPGA internal architecture

• Xilinx FPGA Design Process

• Core Generator

• Synthesis & Implementation, Configuration Flow

• Timing Simulation with ModelSim & ISE 6.1i

• Installation of the Laboratory

• ModelSim Tool Training

• Simulation of 1-bit Adder / Subtracter / Mux  by Gate Level & Data Flow Level in ModelSim

• Simulation of 4-bit Adder/ Subtracter / Mux using 1-bit Adder/Subtracter/Mux by Behavioral Level by using 1-bit in ModelSim

• Xilinx ISE Tool Training

• Training Kits and Flasher Design

• BCD to Seven Segment Decoder